Single ended simpler dual port memory cell

ABSTRACT

A single ended simplex dual port memory cell is described. One port of the memory cell is dedicated for writing operations and the other port of the memory cell is dedicated for reading operations. A bit of data received from the first port can be stored in the memory cell. The second port can detect the memory cell contents substantially simultaneously as the memory cell is storing a bit of data from the first port. Each port is optimized for its respective dedicated operation. In other words, one port is optimized for write operations and the other port is optimized for read operations. Because one port of the memory cell is optimized for write operations and the other port of the memory cell is optimized for read operations, the cell does not require multiple wordline voltages for each port.

This is a continuation divisional of application Ser. No. 08/362,814,filed Dec. 22, 1994, now abandoned.

FIELD OF THE INVENTION

This invention relates to the field of semiconductor memories. Moreparticularly, this invention relates to providing a smaller dual portSRAM memory cell.

BACKGROUND OF THE INVENTION

A typical random access memory (RAM) architecture consists of an arrayof memory cells. Each cell can store one bit of information. The arrayis arranged as rows and columns of memory cells. Each row is alsoreferred to as a wordline. Each column is also referred to as a bitline.A memory device containing such an array with 2^(m) rows and 2^(n)columns can store 2^(m)·n bits of information. If fabrication of such anarray requires one unit of area, then the memory cell density for suchan array is 2^(m)·n cells per unit area.

In systems which require memory devices, storage capacity andoperational speed of the memory are important attributes. From a systemthroughput standpoint, the accessibility of the memory device is anotherimportant attribute. Storage capacity refers to the amount of data thata memory device can store. Operational speed refers to the speed atwhich the memory device can store or retrieve data. Accessibility islargely dependent upon the architecture of the system. Generally, thesystem throughput increases when more than one system device candirectly access the memory device. The system throughput is generallyfurther increased when more than one device can simultaneously accessthe memory.

Since a memory device typically contains one or more arrays of memorycells, the storage capability of a memory device is largely dependentupon the size of a memory cell. The size of a cell given a fixed numberof components will change as fabrication technology evolves. However,any reduction in the size of a memory cell will permit fabrication ofmemory devices containing an increased density of memory cells. Areduction in cell area will permit an increase in an array's celldensity by a factor approaching the reduction factor.

Thus, for example, a cell which uses 40% of the area of another cellwill have a reduction factor of 2.5. Therefore, an array of the smallercells may have a cell density approaching 2.5 times that of an array ofthe larger cells.

Storage capacity is directly related to cell density. Given a fixed unitof area for an array of memory cells, a reduction factor of 2.5 willpermit memory devices constructed with the smaller cells to have up to2.5 times the storage capacity of memory devices constructed with thelarger cells.

System access speed can often be dramatically increased through the useof a dual port memory architecture. A dual port memory has two accessports so that more than one system device may directly access thememory. A single port memory permits direct coupling to only one systemdevice such that other system devices must contend for the port in orderto gain access to the memory. By permitting direct coupling to more thanone system device, overall system performance is usually enhanced sincea dual port architecture decreases the contention for access to a portof the memory.

Examples of memory devices utilizing a dual port memory architectureinclude dual port static random access memories (SRAMs) andfirst-in-first-out ("FIFO") buffers. An integrated circuit dual portmemory device may include an array of dual port memory cells. One suchprior art dual port cell is illustrated in FIG. 1.

Traditional dual port memory cells suffer from a number ofdisadvantages. One disadvantage of the prior art dual port memory cellis that the layout size of such a cell is approximately 2-2.5 times thesize of a single port cell constructed using the same fabricationtechnology. Another disadvantage of the prior art dual port memory cellis that a pair of bitlines are required for each port due to thedifferential nature of the cell.

Another method of achieving the effect of a dual port memory device inpractice is to use an array of single port memory cells inside the dualport memory device. Such a prior art single port memory cell isillustrated in FIG. 2. In this example, the ports of the memory deviceare multiplexed before gaining access to the memory array. Thus twodevices are contending for access at the device level as opposed to atthe level of a memory cell in the array.

One disadvantage of using multiplexed single port memory cells is thatthe multiplexing circuitry uses space which could otherwise be utilizedto construct more memory cells. In addition, the multiplexing functionfor accessing a single port cell is slower than the direct access methodusing a dual port memory cell. This typically results in a sloweroperational speed for the memory device. The slower operational speed ofthe memory tends to negatively affect the throughput of the entiresystem if memory accesses are frequently requested.

SUMMARY AND OBJECTS OF THE INVENTION

A single ended dual port memory cell is described. The memory cell canstore a bit of data received from one of a first port and a second port.The first and second ports can simultaneously detect the stored bit.

The single ended dual port memory cell can be used in applications whereone port is dedicated for read operations and another port is dedicatedfor write operations. In such applications, the single ended dual portmemory cell functions as a single ended simplex dual port memory celland the ports may be optimized for their respective dedicated read orwrite operations.

Other objects, features, and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription that follows below. dr

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

FIG. 1 illustrates a schematic for one prior art differential dual portmemory cell.

FIG. 2 illustrates a schematic for one prior art differential singleport memory cell.

FIG. 3 illustrates a schematic for a single ended dual port memory cell.

FIG. 4 illustrates a schematic for a prior art single ended single portmemory cell.

FIG. 5 illustrates an alternative embodiment for a single ended dualport memory cell.

FIG. 6 illustrates a block diagram of the supporting circuitry for anarray of single ended dual port memory cells.

FIG. 7 illustrates a block diagram of the supporting circuitry for anarray of single ended simplex dual port memory cells.

DETAILED DESCRIPTION

FIG. 3 illustrates the circuit diagram for one embodiment of a singleended dual port static memory cell as implemented using metal oxidesemiconductor (MOS) technology. The cell 300 of FIG. 3 is a staticrandom access memory (SRAM) cell. A dual port memory device may includean array of such cells.

NMOS transistors 350 and 360 serve as pass gates to bitlines 372 and 382of the first 370 and second 380 ports, respectively.

The latch device for storing a bit of data is formed by NMOS transistors310 and 320 and PMOS transistors 330 and 340. FIG. 5 illustrates analternative embodiment which uses resistive load devices 530 and 540instead of the PMOS transistors 330 and 340 of FIG. 3.

Referring to FIG. 3, first port 370 is associated with bitline 372 andwordline 374. First port bitline 372 is used for writing a single bit ofdata to memory cell 300 from the first port 370. First port bitline 372is also used for reading a single bit of information from memory cell300 via the first port 370. First port wordline 374 is used to selectmemory cell 300 for a read or write operation via the first port 370.

The second port operates in a similar fashion. Second port 380 isassociated with bitline 382 and wordline 384. Second port bitline 382 isused for writing a single bit of data to memory cell 300 from the secondport 380. Second port bitline 382 is also used for reading a single bitof information from memory cell 300 via the second port 380. Second portwordline 384 is used to select memory cell 300 for a read or writeoperation via the second port 380.

Both the first and second ports must utilize the same logic basis forstorage in order to ensure that the first and second ports can share thememory cell. In other words, the first and second ports must both useeither a positive or a negative logic system.

In order to ensure that the same logic system is used by both the firstand second ports, the data provided by one of the bitlines (372 or 382)should be inverted. The addition of inverting logic to the supportingcircuitry for the memory array should not consume any substantial areasince the inverting logic may be added at the device port level insteadof at the memory cell level. FIG. 6 illustrates one embodiment of thesupporting circuitry 600 for an array of single ended dual port memorycells 610 in block diagram form. For example, in a 32K×1 bit dual portmemory device, inverting logic might be added to one but not both of thedevice ports. In FIG. 6, the right port data input buffer 622 and theport output buffer and pad driver 624 might include inverting logic toaccomplish the data inversion at the port level. Another embodimentmight utilize an inverting data input driver 632 and an inverting senseamplifier (SAMP) 634. This should be contrasted with requiring invertinglogic for each memory cell of the array 610.

Such inverting logic is generally faster and tends to consume less areathan the multiplexing circuitry of a prior art memory device which usesthe multiplexed single port cells as discussed above.

Unless specifically provided for otherwise, the reading and writingexamples will assume a positive logic system with respect to the firstport 370. This means that a high logic level or "1" is represented by avoltage greater in magnitude than the voltage representing a low logiclevel or"0." The voltage level at node 351 indicates the state of thecell. Thus for purposes of example, the supporting circuitry isinverting bitline 382 signals (and not signals on bitline 372).

Typically there may be problems associated with reading or writingsingle ended single port memory cells as contrasted with differentialcells. Referring to FIG. 2, a pair of complementary signals are suppliedto differential memory cell 200 via bitlines 272a and 272b during awrite operation. This helps to ensure that memory cell 200 can "flip" orchange states when the cell contents do not match the value that is tobe stored. For example, if a "1" is to be stored, bitline 272a willcarry a logical "1" and bitline 272b will carry a logical "0." Whenwordline 274 is brought to a high level, one side of cell 200 is"pushed" and the other side will be "pulled" to ensure that the cellstores a logical "1." This is the differential or dual-ended nature ofthe cell during a write operation. In contrast, referring to the singleended cell of FIG. 3, instead of a combined "push" and "pull" action oncell 300 during a write operation there is only either a "push" or a"pull" from one port or the other. This is because there is only onebitline associated with each port and the ports operate independentlyfrom each other. Since a write or a read operation of cell 300 takesplace by using a single bitline, other techniques must be utilized toensure that memory cell 300 can be forced to change states and retainthe stored value. Otherwise cell 300 may be unable to latch a valuewritten to it during a write operation.

A differential memory cell is generally built to maintain cell stabilityduring read operations and the ability to latch a value during writeoperations without the use of special supporting circuitry such ascharge pumps and reference signals. A single ended memory cell may beunable to latch the value written to it for write operations whichutilize normal supporting circuitry. One embodiment of a prior artsingle ended single port cell is illustrated in FIG. 4. In FIG. 4, theinability to latch a value written to cell 400 is due to the lowconductance (high resistance) of pass gate transistor 450 as compared tothat of transistor 410.

Referring to the prior art differential memory cell 200 in FIG. 2, theratio of the gate width-to-length ratio of transistor 210 to the gatewidth-to-length ratio of transistor 250 is in the range of approximately1.5-2.0. The ratio of the gate width-to-length ratio of transistor 220to that of 260 is approximately the same as the ratio of the gatewidth-to-length ratio of transistor 250 to the gate width-to-lengthratio of transistor 210. The ratio of the width-to-length ratio of thepull down or latch device (i.e., 210) over the effective width-to-lengthratio of the pass gate (i.e., 250) is called the Beta Ratio of thememory cell. Algebraically this equates to ##EQU1## for cell 200. Iftransistors 210 and 250 are constructed with the same gate length, thenthe Beta Ratio is simply the ratio of the gate widths (i.e., W₂₁₀/W₂₅₀). Although FIG. 2 illustrates two pass gates (250, 260) and twopull down devices (210, 220), there is only one Beta Ratio for the cellbecause the cell is typically symmetrical. In other words, the loaddevices 240 and 230 have identical characteristics and the widths,lengths, and operational characteristics of transistors 210 and 250 areidentical to those of transistors 220 and 260, respectively. Thus theBeta Ratio for prior art cell 200 is typically in the range of 1.5-2.0.The Beta Ratio for a prior art cell utilizing resistive loads istypically 2.5-3.0. In other words, the gate width-to-length ratio oftransistors 210 and 220 is up to three times that of transistors 250 and260, respectively, in the prior art differential cell 200 when resistiveloads are used. Utilizing a Beta Ratio of 1.5-2.0 in the single endedcell 400 of FIG. 4, can lead to the inability to properly latch valueswritten to the cell during a write operation.

One method for overcoming this inability to properly latch values forcell 400 is to use a wordline boost circuit to increase the conductance(reduce the resistance) of transistor 450 during a write operation.Increasing the conductance of transistor 450 will permit a writeoperation which utilizes a single bitline 472. Applying a voltagegreater than V_(CC) to wordline 474 will increase the conductance oftransistor 450. During a read operation a normal voltage (e.g., V_(CC))is applied to the wordline 474 and the cell remains stable for the readoperation.

Another method involves changing the Beta Ratio of memory cell 400 fromthat of a typical differential memory cell. For example, a memorydesigner may choose input pass gate transistor 450 to be twice the sizeof 410 and 420. By doubling the size of transistor 450 with respect totransistors 410 and 420, the memory designer has reduced the Beta Ratioof the memory cell to approximately 0.5. This will permit writeoperations which use normal supporting circuitry and normal wordlinevoltages (e.g., V_(CC)). However, decreasing the resistance of pass gate450 generally causes the memory cell to be unstable with respect to readoperations. In other words, a read operation may cause the cell to losethe value stored. Cell stability can be maintained by decreasing theconductance of pass gate transistor 450 during the read operation. Theconductance of pass gate transistor 450 can be decreased by using avoltage less than V_(CC) on wordline 474 during the read operation.

The methods applied to overcome reading or writing difficulties for thesingle ended single port cell 400 may be extended to the single endeddual port memory cell 300 illustrated in FIG. 3. Thus the memory celldesigner may choose to maintain a Beta Ratio similar to that of theprior art differential memory cells or the memory designer may choose todesign a cell with a lower Beta Ratio. Accordingly, the designer willhave to modify the supporting circuitry for the write operation or theread operation.

To execute a read operation of memory cell 300 from the first port 370,wordline 374 is set to a logical high level. If cell 300 is designed tohave a Beta Ratio similar to that of the prior differential memorycells, the wordline voltage should be approximately V_(CC). Otherwise,if cell 300 is designed with a lower Beta Ratio, the supportingcircuitry should provide a voltage less than V_(CC) for the wordline 374voltage. This turns bitline pass gate transistor 350 on to permit a databit to be communicated from cell 300 to bitline 372. Assuming a positivelogic system with respect to the first port, if cell 300 contains alogical "1," transistors 340 and 320 will be on and transistors 330 and310 will be off. Since transistor 340 is on and transistor 310 is off, avoltage approaching V_(CC) will be imposed on bitline 372 from node 351.

In the event that cell 300 contains a logical "0," transistors 310 and330 are on and transistors 320 and 340 are off. Since transistor 310 ison and transistor 340 is off, a voltage approaching V_(SS) will beimposed on bitline 372 from node 351.

The read operation as executed from the second port is similar exceptthat the memory cell is referenced as positive logic with respect to thefirst port. To execute a read operation of cell 300 from the second port380, wordline 384 is set to a logical high level. This permits bitlinepass gate transistor 360 to turn on to permit a data bit to becommunicated from cell 300 to bitline 382. Assuming a positive logicsystem with respect to the first port, transistors 340 and 320 will beon and transistors 330 and 310 will be off when cell 300 contains alogical "1," just as when the read operation is performed from the firstport. Since transistor 320 is on and transistor 330 is off, a voltageapproaching V_(SS) will be imposed on bitline 382. Since V_(SS)represents a logical "0," the supporting circuitry for the memory arraywill have to invert the data from bitline 382 in order to accuratelyrepresent the contents of memory cell 300. As discussed previously,inverting logic could be provided at the level of the second device portas opposed to a cell by cell basis. Another embodiment might utilizeinverting logic at an intermediate level, such as with groups ofbitlines.

One manner in which to execute a write operation is illustrated asfollows. In order to execute a write operation to port 370, wordline 374is raised to a logical high level. If cell 300 is designed with atypical differential memory cell Beta Ratio, the wordline 374 voltagemay need to exceed V_(CC). Otherwise if cell 300 is designed to have asmaller Beta Ratio, the wordline 374 voltage is approximately V_(CC).This permits bitline pass gate transistor 350 to turn on with sufficientconductance so that a data bit to be written may be communicated frombitline 372 to cell 300. Assuming cell 300 is currently storing alogical level "0" (voltage at node 351 approaching V_(SS)), if a logicallevel "1" is to be written to cell 300, the logical "high" voltage onbitline 372 begins to raise the voltage at node 351. As the voltage atnode 351 increases, the conductance of PMOS transistor 330 decreases andthe conductance of NMOS transistor 320 increases. This decreases thevoltage at node 361. As the voltage at node 361 decreases, theconductance of NMOS transistor 310 decreases and the conductance of PMOStransistor 340 increases. The voltage at node 351 increases as theconductance of NMOS transistor 310 decreases. Thus a positive feedbackcycle is established and continues until transistors 310 and 330 areturned off and transistors 320 and 340 are turned on such that node 351is latched at a voltage level approaching V_(CC). Similarly, node 361 islatched at a voltage level approaching V_(SS). If the cell was storing a"1" before the operation, then node 351 would simply remain at a levelapproaching V_(CC). Regardless of the previous state of the cell, cell300 is now latched in a logical "1" state such that the voltage imposedon bitline 372 approaches V_(CC).

To ensure that this method of writing to memory cell 300 will functionproperly, pass gate transistor 350 is chosen so that it has a small "on"resistance (drain to source resistance) compared to the "on" resistanceof 310. The same relationship holds true for the "on" resistance of passgate transistor 360 and transistor 320. This will permit writing tomemory cell 300 using typical supporting circuitry and wordline voltages(V_(CC)). An alternative embodiment would be to maintain the same BetaRatio as a standard differential memory cell. As stated previously, thismay require the supporting circuitry to provide voltages greater thanV_(CC) on the wordlines 374 or 384 during a write operation.

Transistors 330 and 340 (or resistive load devices in an alternativeembodiment) are large enough to ensure cell stability while meetingleakage constraints determined by the memory designer. One embodimentmight be PMOS transistors 340 and 330 which have an "on" resistance ofapproximately twice that of the "on" resistance of NMOS transistors 310and 320, respectively. Another embodiment as illustrated in FIG. 5 mightinclude resistive load devices 540 and 530 which have a resistance whichis twice that of the "on" resistance of transistors 510 and 520,respectively.

Referring back to FIG. 3, the process for writing a logical "0" to port370 is similar to the process for writing a logical "1." Wordline 374 israised to a logical high level to permit a data bit to be communicatedfrom bitline 372 to cell 300. If the memory cell 300 is designed with atypical differential memory cell Beta Ratio, the wordline 374 voltagemay need to exceed V_(CC). Otherwise if the memory cell 300 is designedto have the smaller Beta Ratio, the wordline 374 voltage isapproximately V_(CC). This permits bitline pass gate transistor 350 toturn on with sufficient conductance so that a data bit to be written maybe communicated from bitline 372 to cell 300. Assuming cell 300 iscurrently storing a logical level "1" (voltage at node 351 approachingV_(CC)), if a logical level "0" is to be written to cell 300, thelogical "low" voltage on bitline 372 begins to lower the voltage at node351. As the voltage at node 351 decreases, the conductance of PMOStransistor 330 increases and the conductance of NMOS transistor 320decreases. This increases the voltage at node 361. As the voltage atnode 361 increases, the conductance of NMOS transistor 310 increases andthe conductance of PMOS transistor 340 decreases. The voltage at node351 decreases as the conductance of NMOS transistor 310 increases. Thusa positive feedback cycle is established and continues until transistors310 and 330 are turned on and transistors 320 and 340 are turned offsuch that node 351 is latched at a voltage level approaching V_(SS).Similarly, node 361 is latched at a voltage level approaching V_(CC). Ifthe cell was storing a "0" before the operation, then node 351 wouldsimply remain at a level approaching V_(SS). Regardless of the previousstate of the cell, cell 300 is now latched in a logical "0" state suchthat the voltage imposed on bitline 372 approaches V_(SS).

The process for executing a write operation to port 380 requires raisingwordline 384 to a logical high level to permit a data bit to becommunicated from bitline 382 to cell 300. Data to be written to port380 should be inverted since the memory cell is based on positive logicwith respect to port 370. For example, when a logical "1" is to bewritten to the second port of a memory device, the supporting circuitryfor the array should invert the signal so that a logical "0" ispresented to port 380 of cell 300. Assuming cell 300 is currentlystoring a logical level "0" (voltage at node 361 approaching V_(CC)),the logical "low" voltage on bitline 382 begins to lower the voltage atnode 361. From this point, the cell operates similarly to the way inwhich a "1" was written to port 370. As the voltage at node 361decreases, the conductance of PMOS transistor 340 increases and theconductance of NMOS transistor 310 decreases. This increases the voltageat node 351. As the voltage at node 351 increases, the conductance ofNMOS transistor 320 increases and the conductance of PMOS transistor 330decreases. The voltage at node 361 decreases as the conductance of NMOStransistor 320 increases. Thus a positive feedback cycle is establishedand continues until transistors 310 and 330 are turned off andtransistors 320 and 340 are turned on such that node 361 is latched at avoltage level approaching V_(SS). Similarly, node 351 is latched at avoltage level approaching V_(CC). If the cell was storing a "1" beforethe operation, then node 361 would simply remain at a level approachingV_(SS). Regardless of the previous state of the cell, cell 300 is nowlatched in a logical "1" state.

The operation for using port 380 to store a logical "0" using the secondport of a memory device is similarly executed in that the data bit isinverted by supporting circuitry such that a logical "1" is carried bybitline 382 to the cell.

Some memory applications require writing only to one port and readingonly from the other port. In this case the single ended dual port memorycell can be optimized to avoid applying multiple voltages on thewordlines. A dual port memory cell which permits read and writeoperations at each port is referred to as a duplex cell. If a dual portmemory cell has one port dedicated for writing and another portdedicated for reading, then the cell is referred to as a simplex cell.Examples of memory applications which require writing only to one portand reading only from another port include input buffers, outputbuffers, and first-in-first-out buffers (FIFOs).

In the duplex dual port memory cell, symmetry with respect to thedevices associated with each port is important because writing andreading operations take place at each port. Introduction of asymmetryinto a duplex cell may create differences in reading or writingcapabilities at each port. However, by introducing device asymmetry,first port 370 may be optimized for writing and second port 380 may beoptimized for reading so that cell 300 may be used effectively as asingle ended simplex dual port memory cell. The supporting circuitrywould not need to provide multiple voltages on each port wordline ifcell 300 were a single ended simplex dual port memory cell.

For a single ended simplex dual port memory cell, write port transistor350 is intentionally sized larger (i.e., lower resistance) thantransistor 310. By choosing a larger transistor 350, cell 300 isintentionally destabilized with respect to write port 370 so that aboost voltage (i.e., greater than V_(CC)) is not required on wordline374 for a write operation.

Similarly, read port transistor 360 is intentionally sized smaller(i.e., greater resistance) than transistor 320. By choosing a smallerpass gate transistor (360), port 380 can facilitate stable readingwithout the use of voltages less than V_(CC) on wordline 384.

Since drain-to-source resistance is inversely proportional to transistorgate widths (assuming a fixed gate length), the higher resistancedevices might be fabricated as small as possible and the sizes of theless resistive devices may be chosen after determining the size of thesmaller components. In one embodiment, transistors 310, 330, 340, and360 might be chosen to have the same device geometries (i.e., gatewidths are equal and gate lengths are equal). Pass gate 350 is chosen tohave a significantly greater gate width than NMOS transistor 310.Conversely, NMOS transistor 320 is chosen to have a significantlygreater gate width than pass gate 360. Thus using a process that permitsminimum geometries of 0.5 microns, PMOS transistors 330 and 340 mighthave gate widths of 0.5 microns and gate lengths of 0.5 microns. Readoperation pass gate 360 and transistor 310 might have gate widths of 0.5microns and gate lengths of 0.5 microns. Write operation pass gate 350and transistor 320 might have gate widths of 1.2 microns and gatelengths of 0.5 microns. Due to the asymmetry, cell 300 now has a writeport Beta Ratio and a read port Beta Ratio which are no longer equal.

For the single ended simplex dual port cell 300, a read operation isaccomplished through port 380. Transistor 360 has a greaterdrain-to-source resistance than 320 in order to keep the cell stablewith respect to the read port when bitline 382 is carrying V_(CC) andnode 361 is latched at a value approaching V_(SS). Thus even if bitline382 is carrying a voltage approaching V_(CC) when pass gate 360 isselected by wordline 384, the cell contents will not change (i.e., node361 will not change from V_(SS) to V_(CC)). However, if node 361 islatched at a value approaching V_(CC) and bitline 382 is carryingV_(SS), pass gate 360 may not have sufficient resistance to prevent cell300 from changing states. This might be circumvented by ensuring thatthe read port bitline 382 is precharged to carry V_(CC) prior to turningon wordline 384.

The single ended dual port memory cell of FIG. 3 will permitsimultaneous access from both ports 370 and 380. As a duplex cell, thememory cell will permit simultaneous read operations from both ports.Cell 300 may be simultaneously accessed by one port executing a readoperation and the other port executing a write operation.

Cell 300 may not operate predictably when each port is trying to write adifferent value although this is not of concern with a simplex cell.Also, when a read operation from one port is executed at the same timethat a write operation is executed to the other port, the retrievedvalue may not be the expected value. These two situations, however, maybe taken care of in a number of ways. One way is to simply ignore thefact that the data may not be accurate. Another way is to resolve suchcontention with the supporting circuitry by not permitting simultaneousaccess under these conditions.

A block diagram of supporting circuitry 700 for an array of single endedsimplex dual port memory cells is illustrated in FIG. 7. The invertingsingle ended sense amplifier 734 accomplishes the data inversion at thedevice level in this example. The data inversion is associated with thedevice read port (output buffer and pad driver 724). In the case of aFIFO structure, the X (row) and Y (column) addresses may be provided bypointers. Since read and write operations are exclusively conducted onlyon dedicated ports, the diagram is somewhat less complicated than thesupporting circuitry diagram illustrated in FIG. 6.

By comparing FIGS. 1, 2, and 3, several advantages should becomeapparent. FIG. 1 illustrates a prior art dual port memory cell 100 whichrequires two latch transistors (110, 120), four bitline pass gatetransistors (130,140, 150, 160) and two resistive loads (162 and 164).The four bitline pass gates permit asynchronous read and writeoperations to occur from two separate, asynchronous ports, 170 and 180.In contrast, the embodiment illustrated in FIG. 3 only requires fourlatch transistors and two pass gate transistors. Thus the dual port cell300 can achieve the functionality of dual port cell 100 with fewermemory cell components.

Another distinction between the prior art cells of FIGS. 1 and 2 and thecircuit of FIG. 3 is that FIGS. 1 and 2 illustrate differential or dualended memory cells (100 and 200), whereas FIG. 3 illustrates a singleended memory cell, 300. The contents of a memory cell are typicallydetected by a sense amplifier coupled to the cell. In FIG. 2, the stateof the memory cell is detected by measuring the difference between asignal presented on bitline 272a and the complementary signal presentedon 272b by memory cell 200. Thus the sense amplifier detects thecontents of the prior art memory cell by measuring the potentialdifference between bitlines 272a and 272b. Likewise in FIG. 1, the stateof the memory device is determined by measuring the potential differencebetween bitlines 172a and 172b for port 170 or by measuring thepotential difference between bitlines 182a and 182b for port 180. InFIG. 3, however, the state of cell 300 may be determined by comparingthe potential sensed on bitlines 372 or 382 to a reference voltage(e.g., V_(CC), V_(SS), or signal ground) instead of to othercomplementary signals provided by the memory cell (e.g., thecomplementary bitlines 172b and 182b of FIG. 1 or 272b of FIG. 2).

A memory device utilizing single ended simplex dual port memory cellscan provide (1) the accessibility benefits typically associated withdual port cells as shown in FIG. 1 while simultaneously achieving (2)the storage capacity of a memory device constructed with the single portmemory cell structure as illustrated in FIG. 2. Furthermore, since thesimplex cell may be optimized for both read and write operations, thememory designer may avoid the supporting circuitry modificationsrequired for providing multiple wordline voltages.

In the foregoing specification, the invention has been described withreference to specific exemplary embodiments thereof. It will, however,be evident that various modifications and changes may be made theretowithout departing from the broader spirit and scope of the invention asset forth in the claims. The specification and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

What is claimed is:
 1. A single ended simplex dual port memory cellcomprising:a read transistor for reading data to the memory cell, havinga first gate width-to-length ratio; a write transistor for writing datato the memory cell, having a second gate width-to-length ratio; a firstpass gate transistor having a third gate width-to-length ratio,receiving a first input and being coupled to the read transistor and toa first port; and a second pass gate transistor having fourth gatewidth-to-length ratio, receiving a second input independent of the firstinput, and coupled to the write transistor and to a second portindependent of the first port, wherein (a) the ratio of (i) the firstgate width-to-length ratio to (ii) the third gate width-to-length ratiois greater than 1.5, and (b) the ratio of (iii) the second gatewidth-to-length ratio to the (iv) fourth gate width-to-length ratio isless than 1.5.
 2. A memory array comprising a plurality of the singleended simplex dual port memory cells of claim
 1. 3. The single endedsimplex dual port memory cell of claim 1, wherein the ratio of thesecond gate width-to-length ratio to the fourth gate width-to-lengthratio is less than or equal to approximately 0.5.
 4. The single endedsimplex dual port memory cell of claim 1, wherein the ratio of the firstgate width-to-length ratio to the third gate width-to-length ratio isgreater than
 2. 5. The single ended simplex dual port memory cell ofclaim 3, wherein the ratio of the first gate width-to-length ratio tothe third gate width-to-length ratio is greater than
 2. 6. The singleended simplex dual port memory cell of claim 1, further comprising:afirst load device receiving a first voltage and coupled to said readtransistor, and a second load device receiving a second voltagediffering from said first voltage, and coupled to said write transistor.7. The single-ended dual port memory cell of claim 1, wherein said firstpass gate transistor has (i) a first source/drain terminal coupled to afirst bitline and (ii) a second source/drain terminal coupled to a gateof said read transistor, and said second pass gate transistor has (iii)a first source/drain terminal coupled to a second bitline and (iv) asecond source/drain terminal coupled to a gate of said write transistor.8. The single ended dual port memory cell of claim 1, further comprisinga first load device receiving a first voltage and coupled to said readtransistor, and a second load device receiving said first voltage andcoupled to said write transistor.
 9. The single ended dual port memorycell of claim 8, wherein said read transistor has (i) a firstsource/drain terminal coupled to said first load device and (ii) asecond source/drain terminal coupled to a second voltage different fromsaid first voltage, and said write transistor has (iii) a firstsource/drain terminal coupled to said second load device and (iv) asecond source/drain terminal coupled to said second voltage.
 10. Thesingle ended simplex dual port memory cell of claim 8, whereina) thefirst load device comprises a third transistor having a gate coupled tothe gate of the read transistor, and b) the second load device comprisesa fourth transistor having a gate coupled to the gate of the writetransistor.
 11. The single ended simplex dual port memory cell of claim10 wherein the read and write transistors are NMOS transistors and thefirst and second load devices are PMOS transistors.
 12. The single endedsimplex dual port memory cell of claim 10 wherein:a) a gate of the firstpass gate transistor is coupled to a first port wordline and a firstterminal of the first pass gate transistor is coupled to a first portbitline, wherein the first pass gate transistor permits communicationbetween the first port bitline and the memory cell only if the firstport wordline is selected; and b) a gate of the second pass gatetransistor is coupled to a second port wordline and a first terminal ofthe second pass gate transistor is coupled to a second port bitline,wherein the second pass gate transistor permits communication betweenthe second port bitline and the memory cell only if the second portwordline is selected.
 13. The single ended simplex dual port memory cellof claim 12, wherein:a) the first pass gate transistor has a gate widthof approximately 0.5 microns and a gate length of approxim ately 0.5microns; b) the read transistor has a gate width of approximately 0.5microns and a gate length of approximately 0.5 microns; c) the secondpass gate transistor has a gate width of approximately 1.2 microns and agate length of approximately 0.5 microns; and d) the write transistorhas a gate width of approximately 0.5 microns and a gate length ofapproximately 0.5 microns.
 14. The single ended simplex dual port memorycell of claim 13, wherein each of the first and second load devicescomprises a PMOS transistor having a gate width of approximately 0.5microns and a gate length of approximately 0.5 microns.
 15. The singleended simplex dual port memory cell of claim 12, wherein the read andwrite transistors are NMOS transistors, wherein at least one of the passgate transistors is an NMOS transistor.
 16. The single ended simplexdual port memory cell of claim 12, wherein a memory cell supportingcircuitry inverts a bit communicated between the memory cell and one ofa first and second bitlines.
 17. The single ended simplex dual portmemory cell of claim 1, wherein the read and write transistors are NMOStransistors.
 18. The single ended simplex dual port memory cell of claim1, wherein at least one of the first and second pass gate transistors isan NMOS transistor.
 19. The single ended simplex dual port memory cellof claim 6, wherein the read and write transistors are each a first typeof transistor and the first and second load devices are each a secondtype of transistor.
 20. The single ended simplex dual port memory cellof claim 8, wherein the read and write transistors are NMOS transistorsand the first and second load devices are PMOS transistors.
 21. A memorycell, comprising:a first port having an associated first passgate, readtransistor, first wordline and first bitline; and a second port havingan associated second passgate, write transistor, second wordline and asecond bitline, wherein a first resistivity ratio of said first passgateto said read transistor is greater than a second resistivity ratio ofsaid second passgate to said write transistor and said first and secondwordlines are independent of one another.